Courses

LLM and GenAI Integration in EDA Flows

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Leverage LLMs and Generative AI in EDA and VLSI workflows. Covers RTL code generation with LLMs, AI-assisted DRC violation explanation, automated constraint generation, LLM-based verification plan writing, and responsible AI use in semiconductor design. Hands-on with Claude, GPT-4, Cadence AI, and S

AI and ML for Verification Coverage-Driven

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Apply AI/ML techniques to accelerate functional verification coverage closure. Covers ML-based stimulus generation, coverage gap analysis using clustering, reinforcement learning for constrained-random tests, and ML-driven regression optimisation with Cadence vManager AI and JasperGold AI-driven for

AI-Assisted Physical Design and CTS

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Learn how AI/ML is revolutionising Physical Design flows. Covers ML-based placement optimisation, AI-driven clock tree synthesis, reinforcement learning for routing, predictive congestion analysis, and AI-powered timing closure using Cadence Cerebrus and Synopsys DSO.ai.