Courses

Hardware Software Co-design for AI SoCs

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Design AI SoCs with aligned hardware and software stacks. Covers AI SoC architecture trade-offs, compiler (TVM/MLIR) to hardware mapping, driver and runtime design, operator library optimisation, and full-stack performance profiling for next-generation AI inference and training chips.

LLM and GenAI Integration in EDA Flows

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Leverage LLMs and Generative AI in EDA and VLSI workflows. Covers RTL code generation with LLMs, AI-assisted DRC violation explanation, automated constraint generation, LLM-based verification plan writing, and responsible AI use in semiconductor design. Hands-on with Claude, GPT-4, Cadence AI, and S

On-Chip ML Inference Optimisation

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Optimise ML inference performance on custom AI chips. Covers memory hierarchy design for ML (on-chip SRAM, HBM, DRAM), weight compression and caching strategies, operator fusion, pipeline utilisation, data reuse analysis, and power-performance trade-offs on NPU simulators.

AI and ML for Verification Coverage-Driven

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Apply AI/ML techniques to accelerate functional verification coverage closure. Covers ML-based stimulus generation, coverage gap analysis using clustering, reinforcement learning for constrained-random tests, and ML-driven regression optimisation with Cadence vManager AI and JasperGold AI-driven for

AI-Assisted Physical Design and CTS

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Learn how AI/ML is revolutionising Physical Design flows. Covers ML-based placement optimisation, AI-driven clock tree synthesis, reinforcement learning for routing, predictive congestion analysis, and AI-powered timing closure using Cadence Cerebrus and Synopsys DSO.ai.

AI Accelerator Architecture NPU TPU

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Architect AI accelerators (NPU/TPU) for ML inference and training. Covers systolic array architecture, dataflow analysis (weight stationary, output stationary), GEMM/convolution hardware mapping, on-chip SRAM sizing, memory bandwidth analysis, and tiling strategies. Projects design and simulate a si

Neural Network Inference on Edge Chips

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Deploy neural network inference on edge AI chips and embedded platforms. Covers quantisation (INT8/INT4), model pruning, TensorFlow Lite, ONNX runtime, NPU operator mapping, memory bandwidth optimisation, and latency profiling. Hands-on deployment on ARM Ethos NPU, Raspberry Pi 5, and custom edge AI