Courses

Power Management IC (PMIC) Design

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Design complete Power Management ICs (PMIC). Covers LDO regulator design, buck and boost DC-DC converter architectures, bandgap references, charge pumps, battery management circuits, and multi-rail PMIC integration. Design and simulate complete PMIC blocks using Cadence Virtuoso with automotive and

RF/Analog Co-Design

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Design RF circuits in standard CMOS technology. Covers LNA, mixer, VCO, and PA design; S-parameter analysis; noise figure optimisation; impedance matching; and RF layout strategies. Uses Cadence Virtuoso with RF PDKs for simulation and layout. Targeted at wireless SoC, IoT, and RF IC design engineer

I/O Design & High-Speed Serial Interfaces

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Design robust I/O pads and high-speed serial interfaces for modern SoCs. Covers ESD protection circuits, IO pad design, SERDES architecture, LVDS/differential signalling, DDR IO training circuits, and impedance-controlled IO using IBIS models and ADS simulation.

Analog Custom Layout Courses

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Advanced custom layout techniques for high-performance analog and RF ICs. Covers RF layout for inductors and capacitors, deep submicron layout challenges, FinFET layout rules, advanced matching, thermal considerations, and tape-out preparation for 28nm/16nm technology nodes using Cadence Virtuoso.

Analog Mixed Signal Design

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Master Analog/Mixed-Signal (AMS) design for SoC integration. Covers ADC and DAC architectures, PLL design and analysis, bandgap references, LDO regulators, and analog-digital interface challenges. AMS co-simulation using Cadence Virtuoso AMS with Verilog-A models bridges the gap between analog and d

Analog Circuit Design

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Design CMOS analog circuits from first principles using Cadence Spectre. Covers biasing, current mirrors, differential pairs, single-stage and multi-stage amplifiers, op-amp design, bandwidth, stability, and noise analysis. Simulation on real technology PDKs. Essential for analog IC designers and mi

Analog Layout Design

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Learn professional analog IC layout techniques using Cadence Virtuoso. Covers MOSFET layout, matching techniques, common centroid structures, guard rings, shielding, ESD protection layout, DRC/LVS clean design, and parasitic-aware layout optimisation. Targeted at engineers seeking analog, mixed-sign