Courses

BIST – Memory & Logic

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Design and implement BIST structures for memories and logic. Covers MBIST controller design, March test algorithms, memory repair, LBIST architectures, LFSR pattern generators, MISR compactors, and at-speed BIST for automotive ISO 26262 requirements. Uses Mentor Tessent MBIST flow.

ATPG & Test Pattern Generation

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Generate high-quality test patterns using ATPG for maximum fault coverage. Covers stuck-at, transition, and path delay fault models, fault simulation, ATPG pattern optimisation, diagnostic patterns, and tester-ready pattern export. Uses Synopsys TetraMAX and Mentor Tessent on real SoC designs.

Scan Chain Insertion & Compression

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Master scan chain design and test compression. Covers scan flip-flop selection, scan enable routing, EDT/OPMISR compression, scan reordering, X-bounding, and test data volume reduction. Hands-on with Synopsys DFT Compiler and Mentor Tessent for real ASIC scan insertion and ATPG pattern generation.

Design for Testability (DFT)

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Learn the fundamentals of DFT for ASIC and SoC designs. Covers stuck-at and transition fault models, scan chain insertion, test compression (EDT), boundary scan (JTAG/IEEE 1149.1), ATPG fundamentals, and DFT sign-off methodology. Uses Synopsys DFT Compiler and Mentor Tessent flows.