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Improve chip yield through systematic defect engineering and yield analysis. Covers Poisson and negative binomial yield models, defect density measurement, inline inspection (SEM/optical), wafer map analysis, defect-limited vs parametric yield, and DFM impact on yield.
₹50000
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Learn transistor device characterisation and SPICE model extraction. Covers DC/AC measurement techniques, Id-Vg and Id-Vd characterisation, BSIM4/BSIM-CMG model parameters, process corner definition, Monte Carlo variation modelling, and PDK model card creation.
₹50000
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Hours