Courses

Advanced Packaging Wafer Level and 3D-IC

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Learn advanced IC packaging technologies driving the chiplet era. Covers WLP, FOWLP, TSV, 2.5D interposer (CoWoS), 3D stacking, SiP, and thermal/mechanical design for advanced packages. Essential for engineers working on AI, HPC, and mobile SoC packaging roadmaps.

Yield Analysis and Defect Engineering

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Improve chip yield through systematic defect engineering and yield analysis. Covers Poisson and negative binomial yield models, defect density measurement, inline inspection (SEM/optical), wafer map analysis, defect-limited vs parametric yield, and DFM impact on yield.

Device Characterisation and Modelling

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Learn transistor device characterisation and SPICE model extraction. Covers DC/AC measurement techniques, Id-Vg and Id-Vd characterisation, BSIM4/BSIM-CMG model parameters, process corner definition, Monte Carlo variation modelling, and PDK model card creation.

Lithography Fundamentals and EUV

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Understand modern lithography technology driving sub-7nm patterning. Covers optical lithography fundamentals, DUV immersion lithography, EUV technology, OPC and mask data preparation, multiple patterning (SADP/SAQP), and stochastic effects at advanced nodes.

Back-End-of-Line BEOL and Interconnects

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Learn BEOL interconnect fabrication for modern ICs. Covers copper dual-damascene process, barrier layers, low-k dielectric materials, via and metal formation, CMP, RC delay modelling, and electromigration reliability. Essential for Physical Design engineers who need to understand the fabrication bas

CMOS Fabrication Process Front-End

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Deep-dive into CMOS Front-End-of-Line (FEOL) fabrication. Covers wafer preparation, thermal oxidation, diffusion and ion implantation, photolithography patterning, etching, CVD deposition, CMP, and MOSFET formation with impact on device electrical characteristics.

Semiconductor Process Technology Overview

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Understand semiconductor manufacturing process technology from 180nm to sub-5nm nodes. Covers CMOS scaling trends, Moore's Law, front-end and back-end processes, technology node definitions, foundry vs IDM, and the impact of process technology on design rules.

ATE Training

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Learn ATE operation and test program development for semiconductor production test. Covers ATE system architecture (Advantest/Teradyne), device interface boards (DIB/load board), test program creation, parametric and functional test, yield improvement through ATE data analysis, and ATE-DFT co-design