Learn the fundamentals of DFT for ASIC and SoC designs. Covers stuck-at and transition fault models, scan chain insertion, test compression (EDT), boundary scan (JTAG/IEEE 1149.1), ATPG fundamentals, and DFT sign-off methodology. Uses Synopsys DFT Compiler and Mentor Tessent flows.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 395 | ||
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| Short description | Learn the fundamentals of DFT for ASIC and SoC designs. Covers stuck-at and transition fault models, scan chain insertion, test compression (EDT), boundary scan (JTAG/IEEE 1149.1), ATPG fundamentals, and DFT sign-off methodology. Uses Synopsys DFT Compiler and Mentor Tessent flows. | ||
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