Master floorplanning and chip-level planning for ASIC design. Learn die size estimation, aspect ratio selection, macro placement strategies, power ring and stripe design, IO planning, and hierarchical floorplanning techniques. Uses Cadence Innovus with real SoC hierarchical designs for practical ses
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 775 | ||
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| Short description | Master floorplanning and chip-level planning for ASIC design. Learn die size estimation, aspect ratio selection, macro placement strategies, power ring and stripe design, IO planning, and hierarchical floorplanning techniques. Uses Cadence Innovus with real SoC hierarchical designs for practical ses | ||
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