Learn the end-to-end FPGA design flow using Xilinx Vivado and Intel Quartus Prime. Covers RTL simulation, synthesis, technology mapping, placement, routing, timing constraint entry, bitstream generation, and in-system debug (ILA/SignalTap) on real Xilinx Artix-7 and Intel Cyclone V boards.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 687 | ||
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| Short description | Learn the end-to-end FPGA design flow using Xilinx Vivado and Intel Quartus Prime. Covers RTL simulation, synthesis, technology mapping, placement, routing, timing constraint entry, bitstream generation, and in-system debug (ILA/SignalTap) on real Xilinx Artix-7 and Intel Cyclone V boards. | ||
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