Design AI SoCs with aligned hardware and software stacks. Covers AI SoC architecture trade-offs, compiler (TVM/MLIR) to hardware mapping, driver and runtime design, operator library optimisation, and full-stack performance profiling for next-generation AI inference and training chips.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 794 | ||
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| Short description | Design AI SoCs with aligned hardware and software stacks. Covers AI SoC architecture trade-offs, compiler (TVM/MLIR) to hardware mapping, driver and runtime design, operator library optimisation, and full-stack performance profiling for next-generation AI inference and training chips. | ||
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