Accelerate hardware design with High-Level Synthesis using Xilinx Vitis HLS. Covers C/C++ to RTL synthesis, pipeline and dataflow optimisation pragmas, memory partitioning, AXI interface synthesis, and co-simulation. Projects implement ML inference accelerators and DSP kernels for FPGA acceleration.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 503 | ||
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| Short description | Accelerate hardware design with High-Level Synthesis using Xilinx Vitis HLS. Covers C/C++ to RTL synthesis, pipeline and dataflow optimisation pragmas, memory partitioning, AXI interface synthesis, and co-simulation. Projects implement ML inference accelerators and DSP kernels for FPGA acceleration. | ||
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