Leverage LLMs and Generative AI in EDA and VLSI workflows. Covers RTL code generation with LLMs, AI-assisted DRC violation explanation, automated constraint generation, LLM-based verification plan writing, and responsible AI use in semiconductor design. Hands-on with Claude, GPT-4, Cadence AI, and S
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 513 | ||
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| Short description | Leverage LLMs and Generative AI in EDA and VLSI workflows. Covers RTL code generation with LLMs, AI-assisted DRC violation explanation, automated constraint generation, LLM-based verification plan writing, and responsible AI use in semiconductor design. Hands-on with Claude, GPT-4, Cadence AI, and S | ||
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