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Low Power Design Course

Low Power Design Course

₹25000

₹50000

Design power-efficient ICs with advanced low-power techniques. Covers clock gating, power gating, multi-voltage domain design, UPF/CPF power intent, DVFS strategies, retention flops, isolation cells, and level shifters. Essential for engineers working on mobile SoCs, automotive ICs, and IoT chip des

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Has discount
Expiry period Lifetime
Made in English
Last updated at Sun Apr 2026
Level
Advanced
Total lectures 0
Total quizzes 0
Total duration Hours
Total enrolment 0
Number of reviews 968
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Short description Design power-efficient ICs with advanced low-power techniques. Covers clock gating, power gating, multi-voltage domain design, UPF/CPF power intent, DVFS strategies, retention flops, isolation cells, and level shifters. Essential for engineers working on mobile SoCs, automotive ICs, and IoT chip des
Outcomes
  • Understand core concepts of Low Power Design VLSI UPF CPF Techniques
  • Apply practical workflows in Physical Design
  • Build job-ready skills for VLSI Design Courses
  • Work with low power design
  • Work with power gating
  • Work with clock gating
  • Work with multi-voltage
  • Work with UPF
Requirements
  • Basic understanding of electronics and circuits
  • A laptop/desktop with stable internet
  • Suitable for professionals
  • Recommended for pd engineer
  • Tools access can be enabled with this course