Understand memory compiler design and integration for ASIC chips. Covers SRAM architecture, memory compiler configuration, timing model interpretation, wrapper RTL design, memory BIST integration, and memory redundancy. Hands-on use of ARM Memory Compiler and Cadence Genus memory integration flows.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 882 | ||
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| Short description | Understand memory compiler design and integration for ASIC chips. Covers SRAM architecture, memory compiler configuration, timing model interpretation, wrapper RTL design, memory BIST integration, and memory redundancy. Hands-on use of ARM Memory Compiler and Cadence Genus memory integration flows. | ||
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