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On-Chip ML Inference Optimisation

On-Chip ML Inference Optimisation

₹25000

₹50000

Optimise ML inference performance on custom AI chips. Covers memory hierarchy design for ML (on-chip SRAM, HBM, DRAM), weight compression and caching strategies, operator fusion, pipeline utilisation, data reuse analysis, and power-performance trade-offs on NPU simulators.

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Has discount
Expiry period Lifetime
Made in English
Last updated at Sun Apr 2026
Level
Advanced
Total lectures 0
Total quizzes 0
Total duration Hours
Total enrolment 0
Number of reviews 753
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Short description Optimise ML inference performance on custom AI chips. Covers memory hierarchy design for ML (on-chip SRAM, HBM, DRAM), weight compression and caching strategies, operator fusion, pipeline utilisation, data reuse analysis, and power-performance trade-offs on NPU simulators.
Outcomes
  • Understand core concepts of On-Chip ML Inference Optimisation VLSI Bandwidth NPU
  • Apply practical workflows in Accelerator Architecture
  • Build job-ready skills for AI / ML for Hardware Courses
  • Work with on-chip ML
  • Work with inference optimisation
  • Work with bandwidth
  • Work with memory hierarchy
  • Work with weight compression
Requirements
  • Basic understanding of electronics and circuits
  • A laptop/desktop with stable internet
  • Suitable for professionals
  • Recommended for ai chip engineer
  • Tools access can be enabled with this course