Deep-dive into PCIe Gen5 at 32GT/s. Covers Gen5 physical layer improvements, signal integrity challenges, equalization, FEC, PCIe 5.0 spec changes, and interaction with CXL 2.0. Targeted at DV and hardware engineers in data centre and AI accelerator companies.
Learn more| Has discount |
 |
||
|---|---|---|---|
| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
| Level |
|
||
| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
| Total enrolment |
0 |
||
| Number of reviews | 324 | ||
| Avg rating |
|
||
| Short description | Deep-dive into PCIe Gen5 at 32GT/s. Covers Gen5 physical layer improvements, signal integrity challenges, equalization, FEC, PCIe 5.0 spec changes, and interaction with CXL 2.0. Targeted at DV and hardware engineers in data centre and AI accelerator companies. | ||
| Outcomes |
|
||
| Requirements |
|