Design robust Power Delivery Networks (PDN) for high-performance ICs. Covers PDN impedance analysis, power mesh design, decoupling capacitor placement, bump assignment for flip-chip designs, and PDN simulation using Cadence Voltus. Includes advanced topics on package-chip co-design and chiplet PDN c
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 600 | ||
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| Short description | Design robust Power Delivery Networks (PDN) for high-performance ICs. Covers PDN impedance analysis, power mesh design, decoupling capacitor placement, bump assignment for flip-chip designs, and PDN simulation using Cadence Voltus. Includes advanced topics on package-chip co-design and chiplet PDN c | ||
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