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RISC-V Architecture & Design

RISC-V Architecture & Design

₹25000

₹50000

Design a complete RISC-V processor from scratch. Covers RISC-V ISA (RV32I/RV64I), 5-stage pipeline design, hazard detection, memory subsystem, interrupt handling, and SoC integration. Final project synthesises a full RISC-V core on FPGA and targets a standard cell library for ASIC tape-out.

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Has discount
Expiry period Lifetime
Made in English
Last updated at Sun Apr 2026
Level
Advanced
Total lectures 0
Total quizzes 0
Total duration Hours
Total enrolment 0
Number of reviews 545
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Short description Design a complete RISC-V processor from scratch. Covers RISC-V ISA (RV32I/RV64I), 5-stage pipeline design, hazard detection, memory subsystem, interrupt handling, and SoC integration. Final project synthesises a full RISC-V core on FPGA and targets a standard cell library for ASIC tape-out.
Outcomes
  • Understand core concepts of RISC-V Architecture SoC Design RTL Pipeline
  • Apply practical workflows in RTL Design
  • Build job-ready skills for VLSI Design Courses
  • Work with RISC-V
  • Work with processor design
  • Work with SoC
  • Work with instruction set
  • Work with pipeline
Requirements
  • Basic understanding of electronics and circuits
  • A laptop/desktop with stable internet
  • Suitable for professionals
  • Recommended for rtl / soc engineer
  • Tools access can be enabled with this course