Develop embedded software for RISC-V processors. Covers RISC-V toolchain setup, bare-metal startup code, privilege levels (M/S/U mode), OpenSBI, RISC-V Linux bring-up, and RISC-V assembly. Labs use SiFive HiFive and ESP32-C3 hardware.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 571 | ||
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| Short description | Develop embedded software for RISC-V processors. Covers RISC-V toolchain setup, bare-metal startup code, privilege levels (M/S/U mode), OpenSBI, RISC-V Linux bring-up, and RISC-V assembly. Labs use SiFive HiFive and ESP32-C3 hardware. | ||
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