Master scan chain design and test compression. Covers scan flip-flop selection, scan enable routing, EDT/OPMISR compression, scan reordering, X-bounding, and test data volume reduction. Hands-on with Synopsys DFT Compiler and Mentor Tessent for real ASIC scan insertion and ATPG pattern generation.
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| Expiry period | Lifetime | ||
| Made in | English | ||
| Last updated at | Sun Apr 2026 | ||
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| Total lectures | 0 | ||
| Total quizzes | 0 | ||
| Total duration | Hours | ||
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| Number of reviews | 649 | ||
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| Short description | Master scan chain design and test compression. Covers scan flip-flop selection, scan enable routing, EDT/OPMISR compression, scan reordering, X-bounding, and test data volume reduction. Hands-on with Synopsys DFT Compiler and Mentor Tessent for real ASIC scan insertion and ATPG pattern generation. | ||
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