Compare with 1 courses

Synthesis with theory + practical (cadence genus tool)

Synthesis with theory + practical (cadence genus tool)

₹12500

₹25000

Master VLSI logic synthesis from RTL to gate-level netlist using Cadence Genus with full theory and practical labs. Covers synthesis flow setup, SDC constraint writing, timing and area optimisation, technology mapping, and QoR analysis. Hands-on sessions use real standard cell libraries at 28nm/14nm

Learn more
Has discount
Expiry period Lifetime
Made in English
Last updated at Sun Apr 2026
Level
Intermediate
Total lectures 0
Total quizzes 0
Total duration Hours
Total enrolment 0
Number of reviews 616
Avg rating
Short description Master VLSI logic synthesis from RTL to gate-level netlist using Cadence Genus with full theory and practical labs. Covers synthesis flow setup, SDC constraint writing, timing and area optimisation, technology mapping, and QoR analysis. Hands-on sessions use real standard cell libraries at 28nm/14nm
Outcomes
  • Understand core concepts of VLSI Synthesis Cadence Genus Theory Practical
  • Apply practical workflows in Physical Design
  • Build job-ready skills for VLSI Design Courses
  • Work with logic synthesis
  • Work with Cadence Genus
  • Work with RTL to netlist
  • Work with synthesis flow
  • Work with SDC constraints
Requirements
  • Basic understanding of electronics and circuits
  • A laptop/desktop with stable internet
  • Suitable for professionals
  • Recommended for pd engineer
  • Tools access can be enabled with this course