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Verilog

Verilog

Free

Become proficient in Verilog for ASIC and FPGA design. Covers all Verilog constructs, synthesis-aware RTL coding, parameterisation, always blocks, generate statements, and testbench writing. Projects design arithmetic units, FIFOs, and state machines targeting real synthesis with Synopsys DC and Cad

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Has discount
Expiry period Lifetime
Made in English
Last updated at Sun Apr 2026
Level
Intermediate
Total lectures 0
Total quizzes 0
Total duration Hours
Total enrolment 0
Number of reviews 375
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Short description Become proficient in Verilog for ASIC and FPGA design. Covers all Verilog constructs, synthesis-aware RTL coding, parameterisation, always blocks, generate statements, and testbench writing. Projects design arithmetic units, FIFOs, and state machines targeting real synthesis with Synopsys DC and Cad
Outcomes
  • Understand core concepts of Verilog HDL Design ASIC FPGA
  • Apply practical workflows in RTL Design
  • Build job-ready skills for VLSI Design Courses
  • Work with Verilog
  • Work with RTL design
  • Work with hardware description language
  • Work with simulation
  • Work with synthesis
Requirements
  • Basic understanding of electronics and circuits
  • A laptop/desktop with stable internet
  • Suitable for professionals
  • Recommended for rtl / dv engineer
  • Tools access can be enabled with this course